1. Field of the Invention
The present invention relates to a data transfer bus provided between a plurality of functional blocks inside an LSI such as a logic LSI (large-scale integrated circuit) or a VLSI (Very large-scale integrated circuit), or between a plurality of LSIs, and more specifically, to a low power consumption data transfer bus, to which a low power consumption technique was applied, for example, such a data transfer bus that is used in a micro-processor, a micro-controller or the like.
2. Description of the Related Art
Recently, the introduction of an LSI to a portable device is becoming very popular, and at the same time, there has been a problem of heat generation of an LSI, particularly, of a high performance type. Under these circumstances, there is an increasing demand for the development of an LSI or a VLSI of a low power consumption type.
An example of effective techniques of achieving a low power consumption is to decrease the power-supply voltage. In general, the power consumption of an LSI or the like is proportional to a square of the power-supply voltage. Therefore, for example, if the power-supply voltage is changed from 5V, which is most widely used at present time, to 3V, which is recently becoming popular, the power consumption decreases to 36% by itself.
However, if the competition between LSI vendors is taken into consideration, the lowering of the power-supply voltage is only the first step of the low power consumption. In order to meet the demand for the low power consumption, all of the levels of design, from the architecture, functions, circuit technique, to the processing technique, must be satisfied. At each level, effective measurements are, for example, to avoid operating a circuit when it is not necessary (to avoid wasting currents) and to avoid an excessive driving force (proportional to the size of a transistor) for the performance regarding the operation speed.
Generally, an LSI of a micro-processor, a micro-controller or the like, has a bus capable of transferring data between a plurality of functional blocks. The bus is connected to a number of functional blocks, and in many cases, drawn around in a wide area inside an LSI chip. Thus, the lowering of the power consumption of the bus greatly contributes to the achievement of the low power consumption of the LSI as a whole.
A conventional example of the low power consumption technique for a bus is a bus dividing method. In this method, one bus is divided into sections by a bus switch circuit, and the bus is operated only when it is needed. As a result, the average load capacitance driven can be decreased, and the power consumption can be lowered.
However, the mode of the above-described division of the bus is not considered in connection with a specific layout on an LSI chip, and therefore the achievement of the low power consumption is not completely realized. As the worst case, it is necessary to drive all the load on the bus. In this case, the load components situated on another side of the bus switch circuit as viewed from the buffer to drive the load, have to be driven via the bus switch circuit, and therefore the operation speed (data transfer speed) of the bus is decreased as compared to the case where the bus is not divided.